Dr. Vasantha M.H


Dr. Vasantha M.H

Contact Information

Low voltage, Low power analog mixed signal circuits, Continuous-time filter Circuits, System on Chip,

Analog Electronic Circuits, Linear Integrated circuits, Digial system design, Linear control systems, VLSI design, Microprocessors

Digital IC Design, VLSI Technology,Active Filter Design, HDL

Degree/Diploma Description year subject
1 M.Tech.   Master Of Technology IIT Madras, Chennai 2003 Microelectronics and VLSI Design
2 Ph.D.   NITK Surathkal. 2014 Low power, Low Voltage Integrated Continuous-time Gm-C filter Circuits

Publication Type: Journal

  1. Publication Category: International B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “System Level Fault-Tolerance Core Mapping and FPGA-based Verification of NoC," Microelectronics Journal, 2017. OCT 2017
  2. Publication Category: International B. Naresh Kumar Reddy, Vasantha.M.H. and Nithin Kumar Y.B., “Hardware Implementation of Fault Tolerance NoC Core Mapping,” Telecommunication Systems (TELS), 2017. OCT 2017
  3. Publication Category: International B. Naresh Kumar Reddy, Vasantha.M.H., and Nithin Kumar Y.B., “High- Performance and Energy-Efficient Fault-Tolerance Core Mapping in NoC," Sustainable Computing, Informatics and Systems, JUN 2017
  4. Publication Category: International 8. S. Ahish, D. Sharma, M. H. Vasantha, and Y. B. N. Kumar “Performance analysis of InGaAs/GaAsP heterojunction double gate tunnel field effect transistor” in Superlattices and Microstructures Volume 103, March 2017, Pages 93-101 MAR 2017
  5. Publication Category: International S. Ahish, M. H. Vasantha, Y. B. N. Kumar and Dheeraj Sharma “Effect of Drain Doping and Temperature Variation on the Performance of Heterojunction Double Gate Tunnel Field Effect Transistor from a 2D ATLAS Simulation” in Journal of Nanoelectronics and Optoelectronics OCT 2016
  6. Publication Category: International DC and Analog/RF performance analysis of Hetero Junction Double Gate Tunnel Field Effect Transistor, IEEE IET Micro and Nano Letters.(Impact Factor:0.89) 2016
  7. Publication Category: International Performance Enhancement of Novel InAs/Si Hetero Double Gate Tunnel Field Effect Transistor Using Gaussian Doping, "IEEE Transactions on Electron Devices". NOV 2015
  8. Publication Category: International Device and Circuit level performance analysis Hetero Junction Double Gate Tunnel Field Transistor,Journal of Superlattices and Microstructures, Elsevier.(Impact Factor: 2.1) 2015
  9. Publication Category: International “Fixed Transconductance Bias Circuit for Low-Voltage Gate/Bulk Driven Transconductors, World scientific Journal of Circuits, Systems and Computers 2014
  10. Publication Category: International Two-Port Transmission Line Parameters Approach for AccurateModeling and Design Centering of Integrated Continuous- Time Filters”, International Journal of Advanced Computer Research (ISSN (print): 2249-7277, ISSN (online): 2277-7970) Volume-2, Number-4, Issue-6, pp:156- 162. DEC 2012
  11. Publication Category: International 20 µW, 500 kHz Continuous-Time Low-Pass Filter in 0.18 µm CMOS Process, International Journal of Industrial Electronics, Control and Robotics, ISSN 2231-4903, Volume 05, No. 01. JAN 2012

Publication Type: Proceedings

  1. Publication Category: International Sumit Khalapure ; Siddharth R. K. ; Nithin Kumar Y. B. ; Vasantha M. H. “Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing” ISVLSI 2017, Page(s):585 – 588 JULY 2017
  2. Publication Category: International Rakhi R. ; Abhijeet D. Taralkar ; Vasantha M. H. ; Nithin Kumar Y. B. “A 0.5 V Low Power OTA-C Low Pass Filter for ECG Detection” ISVLSI july 2017, Page(s):589 - 593 JULY 2017
  3. Publication Category: International Mayur S. M. ; Siddharth R. K. ; Nithin Kumar Y. B. ; Vasantha M. H “Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC” ISVLSI: 2017, Page(s):600 - 603 JULY 2017
  4. Publication Category: International “A Gracefully Degrading and Energy-Efficient Fault Tolerant NoC Using Spare Core” ISVLSI, University of Pittsburgh, USA. JULY 2016
  5. Publication Category: International “Design of Low Power 5-bit Hybrid Flash ADC” ISVLSI, University of Pittsburgh, USA. JULY 2016
  6. Publication Category: International Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor, ISVLSI, university of Pittsburgh, USA. JULY 2016
  7. Publication Category: International “A Fine grained Modular core position on NoC”, IEEE International Conference on Computer Communication and Control (IC4-2015), Medi-Caps Group of Institutions, Indore, M.P.INDIA. AUG 2015
  8. Publication Category: International “Communication Energy constrained spare core on NoC” The Sixth International Conference on Computing, Communications and Networking Technologies (ICCCNT), held from July 13-15, 2015 Dallas, Fort-worth, Texas USA. JULY 2015
  9. Publication Category: International "0.5V, 225nW, 100 Hz Low pass filter in 0.18µm CMOS process" IEEE Advance Computing conference (IACC-15), Bangalore, PP 590-593. JUN 2015
  10. Publication Category: International “Design of High Performance Multiply-Accumulate Computation Unit” IEEE International Advance Computing Conference (IACC-2015), Bangalore, India, June 12-13, 2015. JUN 2015
  11. Publication Category: International “Low Power, High Speed Error Tolerant Multiplier Using Approximate Adders” Accepted in 19th International Symposium on VLSI Design and Test (VDAT) June 26-29, 2015 JUN 2015
  12. Publication Category: International DC and Analog/RF performance analysis of Hetero Junction Double Gate Tunnel Field Effect Transistor, accepted at IWPSD-2015, IISc. 2015
  13. Publication Category: International “Fixed Transconductance Bias Circuit for Low Voltage Bulk-Driven Transconductor“,in proceedings of International Conference on Communication, VLSI and Signal Processing (ICCVSP–2013), Feb.20–22 2013, 271-274. FEB 2013
  14. Publication Category: International "Low Power, 1MHz Low Pass Filter in 0.18 µm CMOS Process”, in proceedings of IEEE Third International Symposium on Electronic System Design, Dec 18–21, 2012, pp.33–37. DEC 2012
  15. Publication Category: International “0.5 V, 36 µWGm-C Butterworth Low Pass Filter in 0.18µm CMOS process”, in proceedings of The Fourth IEEE Asia Symposium on Quality Electronic Design (ASQED– 2012), July 11–12, 2012, pp. 82–85. JULY 2012
  16. Publication Category: International “A 0.5V, 20 µW Pseudo-differential 500 kHz Gm-C Low-Pass Filter in 0.18 µm CMOS Technology”, in proceedings of IEEE International Conference on Devices, Circuits and Systems (ICDCS– 2012), March 15-16, 2012, pp. 76–79. MAR 2012
  17. Publication Category: International “20 µW, 500 kHz Continuous-Time Low- Pass Filter in 0.18 µm CMOS Process”,in proceedings of Second International Engineering Symposium -IES 2012 (KU-MIT-NITK Joint Symposium), March 5– 7, 2012, pp. E1-3-1–E1-3-6. MAR 2012
  18. Publication Category: International "Comparison of RESURF and Superjunction techniques of improving breakdown voltage of power diode using 2 –dimensional simulation” , ICMAT-2003, Singapore. 2003

Month Year Training attended Information
1 DEC 2015 IEP on " System level design on platform FPGA's" at IIT Delhi.
2 AUG 2014 IEEE Authorship workshop held at Bangalore
3 JAN 2014 “Workshop on Next Generation Internet Protocol IPv6” with the Department of Telecommunications, Government of India, in January 2014
4 MAR 2013 IEEE International Conference on Devices, Circuits and Systems (ICDCS– 2012) held at Coimbatore, March 15-16, 2012,
5 FEB 2013 International Conference on Communication, VLSI and Signal Processing (ICCVSP–2013) held at SIT Tumkur, Feb.20–22 2013
6 DEC 2012 IEEE Third International Symposium on Electronic System Design held at BESU, Kolkata, Dec 18–21, 2012
Month Year Training Conducted Information
1 NOV 2014 Two days expert Lecture by Dr. Devesh Dwivedi (Manager, SRAM development system and technology group, IBM India Pvt. Ltd Bangalore, India.) on recent trends & research activity in VLSI design and R&D collaboration with IBM
2 JULY 2014 3 Days National Workshop on "ARM 7 with embedded C programming" at National Institute of Technology Goa for faculties of various technical institutes, July 30-August 1, 2014.